1. Technical Field
The present invention relates to circuit design and verification of circuits. More particularly, the present invention relates to noise analysis circuit modeling. Still more particularly, the present invention relates to noise simulation modeling for electrical circuits.
2. Description of Related Art
In electrical circuits, noise is an extraneous signal that may be capacitively coupled into a digital circuit from other parts of the system. One source of noise is a signal pickup from a changing voltage on another wire, such as a nearby logic signal wire, also known as a xe2x80x9cnetxe2x80x9d, which connects two or more electronic circuit components. For example, a net may be the wiring connecting components together, such as, for example, two or more latches, but not the components themselves. Such noise may also be due to capacitive cooling or ground shift.
When the electrical circuit is a digital circuit, the circuit operates by logically combining signals with binary states, (i.e., xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d), the result which may be presented as an electrical signal to the input of a xe2x80x9clatchxe2x80x9d circuit device which captures the state of the input signal at a time typically defined by the changing state of a xe2x80x9cclockxe2x80x9d signal. These inputs must remain in the active state long enough for the xe2x80x9clatchxe2x80x9d circuitry to respond. The input signal to the latch may be formed by several stages of xe2x80x9ccombinational logicxe2x80x9d circuits which in effect logically combine many logic inputs to form the single input to the latch. If any net comprising the combinational logic circuit incurs noise of sufficient amplitude and duration, it may change state (i.e. from xe2x80x9c0xe2x80x9d to xe2x80x9c1xe2x80x9d or xe2x80x9c1xe2x80x9d to xe2x80x9c0xe2x80x9d), which will be presented to the next stage of a circuit and so on until eventually a state change may take place at the input to the latch. If the latch is clocked while this erroneous state is present, the latch will sample the wrong state and the circuit will have failed by providing the wrong output.
In electrical design, such as semiconductor chip design, it is important to simulate noise which may be induced on a xe2x80x9cvictimxe2x80x9d net of the chip by its neighboring xe2x80x9caggressorxe2x80x9d nets. An aggressor net may be the wire carrying the output from a component (i.e. a latch) to another component (i.e. another latch). Therefore, during the design of such circuits, it is important to simulate such noise situations and to engineer a design for which such noise-induced failures cannot occur.
The common approach of simulating noise-induced failures is to simulate the noise due to each of the relevant aggressor nets on the circuit inputs or sinks connected to a victim net and then to sum all measured outputs to get the total noise experienced by the sink. This is commonly a costly process because a simulation circuit consisting of victim and aggressor circuits must be constructed and simulated for each aggressor net. For a digital chip design with thousands to millions of nets, it may be that all the nets contained on the digital chip are tested for noise, but such extensive testing is not needed in all cases, such as, for example, nets contained in a small region, net which are overdriven, and the like. So the challenge to a designer of digital chip circuitry is the cost versus benefit of noise testing, the costs including, for example, the time and resource expenditures associated with extensive testing. Traditionally, attempts to reduce costs have been made by creating a xe2x80x9csimplexe2x80x9d circuit and employing this circuit to simulate noise for all nets without regard to the particular characteristics of each particular net. Unfortunately, this technique enhances the probability of erroneous findings. Furthermore, techniques such as using rules-of-thumb or analytical expressions have been used, but work for only simple topologies.
Thus, it would be advantageous, to have an improved method and apparatus for an operation which can simulate induced noise on an electrical circuit during the design of such a circuit.
The present invention provides a method, system and apparatus to perform noise analysis of electrical circuits. The method and system partitions an original multi-port circuit to a reduced circuit model having a specific layout configuration. The reduced circuit model may have a variety of configurations. Then an input signal is applied to a first port of the reduced circuit model using the specific layout configuration and an output signal is measured from a second port of the reduced circuit model. The process continues until all input ports which may contribute noise to the circuit are measured and then the results are calculated to determine the total simulated noise output experienced by the circuit. The calculated output results of the reduced circuit model are then used to determine whether the original circuit is designed to withstand the quantity of noise experienced by the reduced circuit model.